1. Field of the Invention
The present invention relates to techniques for reducing leakage current in a memory device, and in particular to the reduction of leakage current in a memory device having memory cells coupled to bit lines, in situations where the memory device enters a power down mode of operation.
2. Description of the Prior Art
A memory device will typically comprise a plurality of memory cells arranged in rows and columns. For each column, a pair of bit lines is typically provided which is coupled to the column of memory cells, and in preferred embodiments is used to write data to, and read data from, individual memory cells within that column. Bit line precharge circuitry is typically used to precharge each pair of bit lines to a predetermined voltage level during a precharge phase, with the pair of bit lines being arranged such that, when a particular memory cell in the corresponding column is selected in an evaluate phase following the precharge phase, a relative change in voltage level between the pair of bit lines indicates the data value stored within the selected memory cell.
When a data processing system enters a power down (also referred to as a power saving) mode of operation, certain components may be shut down completely, with the power to those components being removed, whilst other components may enter an inactive state where they are not actively consuming power (e.g. internal nodes are not changing state), but where the power supply is still maintained to the component. This may be appropriate in order to ensure that the state of the component is not lost during the power down mode. A memory device such as a cache would be a typical example of a component which during a power saving mode of operation may still have the power supply provided to it to ensure that the contents of the cache memory do not need to be stored to external memory before the power down mode is entered. If this was not done, and the power supply was removed, the data in the cache would be lost.
However, when a memory device of the above type is subject to a power saving mode where the power supply is still provided to the device, there is a tendency for some leakage current to flow via the bit lines during the power saving mode.
Up to now, the issue of leakage current has typically not been of significant concern in many implementations. However, as components decrease in size, it has been found that leakage current tends to increase. Hence, it would be desirable to develop techniques which enable a reduction in the leakage current when a memory device is placed in a power saving mode of operation. Clearly, this becomes even more desirable when seeking to develop systems which are increasingly more power efficient.
Viewed from a first aspect, the present invention provides a memory device, comprising: a column of memory cells, each memory cell being arranged to store a data value; a pair of bit lines coupled to said column of memory cells; bit line precharge circuitry for precharging said pair of bit lines to a predetermined voltage level during a precharge phase, the pair of bit lines being arranged such that, when a particular memory cell in said column is selected in an evaluate phase following said precharge phase, a relative change in voltage level between the pair of bit lines indicates the data value stored within the selected memory cell; power down control circuitry arranged when the memory device is to enter a power down mode to prevent the bit line precharge circuitry from precharging said pair of bit lines; and selector circuitry arranged when the memory device is to enter said power down mode to ensure that none of said memory cells in said column are selected.
In accordance with the present invention, a memory device having a column of memory cells, a pair of bit lines coupled to the column of memory cells, and bit line precharge circuitry, is further provided with power down control circuitry arranged, when the memory device is to enter a power down mode of operation, to prevent the bit line precharge circuitry from precharging the pair of bit lines. Further, selector circuitry is arranged when the memory device is to enter the power down mode to ensure that none of the memory cells in the column are selected. By this approach, it is ensured that the bit lines are no longer xe2x80x9cstronglyxe2x80x9d driven to the predetermined voltage level, the use of the term xe2x80x9cstronglyxe2x80x9d in this case being intended to indicate the act of being driven by a xe2x80x9cturned-onxe2x80x9d device. Hence, in effect, this approach leaves the bit lines floating in the power down mode of operation.
Surprisingly, it has been found that this approach significantly reduces the leakage current that would otherwise flow through the bit lines, and the memory cells coupled to those bit lines. On further analysis, the inventors of this invention have realised that this is due to the fact that a path of significant leakage current is altered by taking the above described steps when entering the power down mode of operation, and that this altered path exhibits a significantly increased resistance to current flow when compared with the unaltered leakage current path observed in typical prior art memory devices.
More particularly, it was found that whereas in the typical prior art memory device, the path of significant leakage current passed through the precharge circuitry, bit lines, and particular components of the memory cell, when the memory device was arranged in accordance with the present invention, the path of significant leakage current instead passed via the bit lines between memory cells in a particular column that are storing different data values. This latter path typically has a significantly increased resistance compared with the above described significant leakage current path of prior art memory devices, which leads to the observed reduction in leakage current.
The power down control circuitry may be arranged in a variety of ways, provided that it serves to prevent the bit line precharge circuitry from precharging the pair of bit lines when the memory device enters the power down mode of operation. However, in one embodiment of the present invention, the power down control circuitry is arranged to receive a power down signal indicating whether the power down mode is set and a precharge signal indicating whether the precharge phase is active, and to generate as its output an input signal to the bit line precharge circuitry, such that when the power down signal indicates that the power down mode is set, the output signal from the power down control circuitry is arranged to cause the bit line precharge circuitry to be turned off.
In such an embodiment, the bit line precharge circuitry preferably comprises one or more P type devices, and said power down control circuitry is arranged to apply a logical OR gate function to the power down signal and the precharge signal. In such an embodiment, the precharge signal will be set to a logic 0 level when the apparatus is in the precharge phase and to a logic 1 level when the apparatus is not in the precharge phase, whilst the power down signal will be set to a logic 1 level when the power down mode is to be entered, and will be set to a logic 0 level otherwise. Accordingly, since the power down control circuitry is arranged to apply a logical OR gate function, it is clear that when the power down signal is set to a logic 1 level, a logic 1 signal will be output by the power down control circuitry to the bit line precharge circuitry, and given that the bit line precharge circuitry comprises one or more P type devices, this will cause the bit line precharge circuitry to be turned off.
In an alternative embodiment, the power down control circuitry is positioned in series with the bit line precharge circuitry between the pair of bit lines and the predetermined voltage level, the power down control circuitry being arranged to receive a power down signal indicating whether the power down mode is set and to turn off when the power down signal indicates that the power down mode is set, thereby preventing the bit line precharge circuitry from precharging said pair of bit lines to said predetermined voltage level. Hence, in this embodiment, the power down control circuitry effectively decouples the bit line precharge circuitry from the predetermined voltage level and/or the pair of bit lines when the memory device is to enter the power down mode of operation. In one embodiment, the power down control circuitry may comprise a P type device and the power down signal is arranged to be set to a logic 1 level when the power down mode is to be entered, whereby application of that power down signal as an input to the P type device causes the P type device to be turned off. Preferably, in such embodiments, the P type device is a P type transistor.
It will be appreciated that the above described invention may be applicable to a variety of different memory device structures. However, in preferred embodiments, the memory cells of the memory device are Random Access Memory (RAM). More particularly, in preferred embodiments, each memory cell comprises a cross-coupled pair of inverter circuits for storing a data value.
It will be appreciated that the selector circuitry used to ensure that none of the memory cells in the column are selected when the memory device is to enter the power down mode of operation may take a variety of forms. However, in preferred embodiments, each memory cell is coupled to each bit line in said pair of bit lines via a memory cell select device, the selector circuitry being arranged to ensure that each memory cell select device is turned off when the memory device is in said power down mode.
Whilst it has been found that significant reductions in the leakage current can be obtained by use of embodiments of the present invention as described above, it has been found that further reductions in the leakage current can be obtained by also including within the memory device voltage regulating circuitry arranged when the memory device is to enter the power down mode to reduce the difference between the predetermined voltage level and a reference voltage level. Since each memory cell in preferred embodiments has components coupled between the predetermined voltage level and the reference voltage level, and given that it has been observed by the inventors that the path of significant leakage current when employing techniques in accordance with preferred embodiments of the present invention passes from one memory cell to another memory cell in the column via one of the bit lines, then it has been found that a reduction in the potential difference between the predetermined voltage level and the reference voltage level further serves to reduce the leakage current. In preferred embodiments, the predetermined voltage level is set to a supply voltage VDD, whilst the reference voltage level is set to ground, and in such embodiments the voltage regulating circuitry is arranged to decrease the value of VDD when entering the power down mode in order to decrease the difference between the predetermined voltage level and the reference voltage level.
In one embodiment of the present invention, one pair of bit lines is coupled to each column of memory cells. However, it will be appreciated by those skilled in the art that some memory device architectures include a plurality of pairs of bit lines coupled to each column of memory cells to provide more flexibility in addressing of memory cells, and it will be appreciated that the techniques of preferred embodiments of the present invention are equally applicable to such memory device architectures.
In preferred embodiments, the memory device further comprises: a plurality of said columns of memory cells; a corresponding plurality of said pairs of bit lines; a plurality of word lines, each word line being coupled to one of said memory cells in each column; said selector circuitry being arranged to drive one of said word lines in said evaluate phase to cause the memory cells coupled to that word line to be selected.
In such embodiments, the selector circuitry preferably comprises: a dynamic node coupled to a corresponding word line; dynamic node precharge circuitry arranged during said precharge phase to precharge the dynamic node to a first voltage level; evaluation circuitry arranged to receive a number of input signals and during said evaluate phase to selectively drive the dynamic node to a second voltage level dependent on the input signals; and power down drive circuitry arranged when the selector circuitry is to enter a power down mode to drive the dynamic node to the second voltage level.
Hence, in such preferred embodiments of the present invention, the selector circuitry has a dynamic node, dynamic node precharge circuitry and evaluation circuitry, and is further provided with power down drive circuitry arranged, when the memory device is to enter a power down mode, to drive the dynamic node to the second voltage level. The aim of this is to substantially remove the leakage current that otherwise is observed through the evaluation circuitry due to the difference between the first and second voltage levels. Whilst the approach of causing the power down drive circuitry to drive the dynamic node to the second voltage level when entering a power down mode does result in leakage current occurring through the dynamic node precharge circuitry, due to the potential difference between the first and second voltage levels, it has been found that this leakage current is significantly less than the leakage current typically flowing through the evaluation circuitry. This is due to the fact that in practice the evaluation circuitry typically includes significantly more components placed in parallel between the dynamic node and the second voltage level than the components within the dynamic node precharge circuitry placed between the dynamic node and the first voltage level, and accordingly by ensuring that in the power down mode the potential difference is placed across the dynamic node precharge circuitry rather than the evaluation circuitry, the leakage current occurring during the power down mode can be significantly reduced.
Hence, in accordance with preferred embodiments of the present invention, not only is a reduction in the leakage current flowing via the bit lines of the memory device obtained, but also a reduction in the leakage current occurring within the selector circuitry is also obtained, hence providing a particularly power efficient arrangement.
It should be noted that the approach taken by the inventors of the present invention is entirely counter intuitive, as typically it would be thought desirable to keep the dynamic node at the precharged first voltage level during a power down mode, to reduce the power that needs to be consumed to return the dynamic node to the first voltage level following the exit from the power down mode back to the normal mode of operation. However, the inventors have noted that in many implementations the memory device may be placed into the power down mode of operation for a significant length of time, and have found that the power savings to be obtained by reducing the leakage current in accordance with embodiments of the present invention significantly outweigh the power consumption required to return the dynamic node to the first voltage level upon exiting the power down mode of operation.
In preferred embodiments, the memory device further comprises coupling logic arranged to couple said dynamic node to said corresponding word line, such that in said evaluate phase if said evaluation circuitry drives said dynamic node to said second voltage level, the corresponding word line is not driven. Since in the power down mode of operation, the dynamic node is driven to the second voltage level, then it is clear that the corresponding word line will not be driven in the power down mode of operation.
The power down drive circuitry may be arranged in a variety of ways, provided that it serves to drive the dynamic node to the second voltage when the power down mode is entered. However, in one embodiment of the present invention, the power down drive circuitry comprises first circuitry responsive to a power down signal indicating that the power down mode is set to drive the dynamic node to the second voltage level and second circuitry responsive to said power down signal to prevent the dynamic node precharge circuitry from precharging the dynamic node to the first voltage level. Hence, in such embodiments, a first part of the circuitry is involved in driving the dynamic node to the second voltage level, whilst the second part of the circuitry is responsible for ensuring that the dynamic node precharge circuitry is prevented from precharging the dynamic node back to the first voltage level.
In such embodiments, the first circuitry preferably comprises an N type device connected between the dynamic node and the second voltage level. In one particular implementation, the N type device is an N-type transistor arranged to receive at its gate the power down signal. The power down signal is set to a voltage sufficient to turn the N type transistor on when the power down mode of operation is to be entered, thereby causing the dynamic node to be driven to the second voltage level.
In one embodiment of the present invention, the second circuitry is arranged to receive the power down signal and a precharge signal indicating whether the precharge phase is active, and to generate as its output an input signal to the dynamic node precharge circuitry, such that when the power down signal indicates that the power down mode is set, the output signal from the second circuitry is arranged to cause the dynamic node precharge circuitry to be turned off.
In such an embodiment, the dynamic node precharge circuitry preferably comprises one or more P type devices, and said second circuitry is arranged to apply a logical OR gate function to the power down signal and the precharge signal. In such an embodiment, the precharge signal will be set to a logic 0 level when the apparatus is in the precharge phase and to a logic 1 level when the apparatus is not in the precharge phase, whilst the power down signal will be set to a logic 1 level when the power down mode is to be entered, and will be set to a logic 0 level otherwise. Accordingly, since the second circuitry is arranged to apply a logical OR gate function, it is clear that when the power down signal is set to a logic 1 level, a logic 1 signal will be output by the second circuitry to the dynamic node precharge circuitry, and given that the dynamic node precharge circuitry comprises one or more P type devices, this will cause the dynamic node precharge circuitry to be turned off.
In an alternative embodiment, the second circuitry is positioned in series with the dynamic node precharge circuitry between the dynamic node and the first voltage level, the second circuitry being arranged to turn off when the power down signal indicates that the power down mode is set, thereby preventing the dynamic node precharge circuitry from precharging the dynamic node to the first voltage level. Hence, in this embodiment, the second circuitry effectively decouples the dynamic node precharge circuitry from the first voltage level and/or the dynamic node when the memory device is to enter the power down mode of operation. In one embodiment, the second circuitry may comprise a P type device, and the power down signal is arranged to be set to a logic 1 level when the power down mode is to be entered, whereby application of that power down signal as an input to the P type device causes the P type device to be turned off. Preferably, in such embodiments, the P type device is a P type transistor.
In preferred embodiments, the first voltage level represents a logic 1 level and the second voltage level represents a logic 0 level. However, it will be appreciated that the present invention is equally applicable where the first voltage level represents a logic 0 level and the second voltage level represents a logic 1 level.
In such preferred embodiments where the first voltage level represents a logic 1 level and the second voltage level represents a logic 0 level, then preferably the evaluation circuitry comprises a plurality of N type devices. In preferred embodiments, these N type devices are N type transistors. In preferred embodiments, the plurality of N type transistors consists of a number of sets of one or more N type transistors, with the various sets being located in parallel between the.dynamic node and the second voltage level.
Further, in such preferred embodiments, the dynamic node precharge circuitry preferably comprises one or more P type devices. In preferred embodiments, these one or more P type devices are P type transistors. In one preferred embodiment, the dynamic node precharge circuitry consists of one P type transistor coupled between the dynamic node and the first voltage level.
Whilst it has been found that significant reductions in the leakage current can be obtained by use of embodiments of the present invention as described above, it has been found that further reductions in the leakage current can be obtained by also including within the memory device voltage regulating circuitry arranged when the memory device is to enter the power down mode to reduce the difference between the first voltage level and the second voltage level, thereby reducing leakage current through the dynamic node precharge circuitry. As mentioned previously, when employing the techniques of preferred embodiments of the present invention, the leakage current observed in the selector circuitry occurs predominantly through the dynamic node precharge circuitry and since this leakage current is governed by the potential difference between the first voltage level and the second voltage level, reduction in the potential difference via the voltage regulating circuitry enables the leakage current to be reduced still further. In preferred embodiments, the first voltage level is set to a supply voltage VDD, whilst the second voltage level is set to ground, and in such embodiments the voltage regulating circuitry is arranged to decrease the value of VDD when entering the power down mode in order to decrease the difference between the first voltage level and the second voltage level.
Viewed from a second aspect, the present invention provides a method of operating a memory device to reduce leakage current in a power down mode of operation, the memory device comprising a column of memory cells, each memory cell being arranged to store a data value, a pair of bit lines coupled to said column of memory cells, and bit line precharge circuitry for precharging said pair of bit lines to a predetermined voltage level during a precharge phase, the pair of bit lines being arranged such that, when a particular memory cell in said column is selected in an evaluate phase following said precharge phase, a relative change in voltage level between the pair of bit lines indicates the data value stored within the selected memory cell, the method comprising the steps of
(a) preventing the bit line precharge circuitry from precharging said pair of bit lines when the memory device is to enter a power down mode; and
(b) ensuring that none of said memory cells in said column are selected when the memory device is to enter said power down mode.